An Efficient Design of True Single Phase Clocked Positive Latch Circuit Using Properly Sized MOSFETs and a Static Inverter to Accomplish Charge Storing Capacity During Low Activity Period of Clock Signal

Abstract

For implementation of pipelined circuits, the roles of level-sensitive positive and negative latches are significant instead of edge-triggered registers. To avoid clock overlapping problem, true single phase clocked latches can be utilized which ensures correct pipeline operation. Therefore, in our design we have proposed a design of positive latch circuit controlled by single phase of a clock signal which help to hold the previous state of output without use of any capacitor in order to avoid the problem of capacitive coupling which is a major problem in most of the purely dynamic circuits. Although transistor sizing is very critical for achieving correct functionality of our design, but still to some extent proper sizing has been made with a sacrifice of not getting full swing at output.