Design of a Phase Detector with Improved Performance

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DC Field	Value	Language
dc.contributor.author	Chakraborty, B
dc.contributor.author	Pal, R.R
dc.date.accessioned	2016-12-22T17:09:16Z	-
dc.date.available	2016-12-22T17:09:16Z	-
dc.date.issued	2008
dc.identifier.issn	0972-8791 (Print)
dc.identifier.uri	http://inet.vidyasagar.ac.in:8080/jspui/handle/123456789/770	-
dc.description	213-220	en_US
dc.description.abstract	This paper presents a new type of bipolar analog Phase Detector (PD) using a high speed low voltage Emitter Coupled Logic (ECL) inverters, where positive feedback has been introduced to increase the operating range. Introduction of positive feedback has also reduced the supply voltage requirement. The same technique has been introduced in a NMOS Gilbert phase detector and similar results were obtained. The minimum supply voltage required for both these circuits were 2.1 volts.	en_US
dc.language.iso	en_US	en_US
dc.publisher	Vidyasagar University , Midnapore , West-Bengal , India	en_US
dc.relation.ispartofseries	Journal of Physical Science;Vol 12 [2008]
dc.subject	Phase Detector (PD)	en_US
dc.subject	Voltage Controlled Oscillator (VCO)	en_US
dc.subject	Emitter Coupled Logic (ECL)	en_US
dc.subject	Phase Locked Loop (PLL)	en_US
dc.title	Design of a Phase Detector with Improved Performance	en_US
dc.type	Article	en_US
Appears in Collections:	Journal of Physical Sciences Vol.12 [2008]

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