Synchronous Oscillator Using High Speed Emitter Couple Logic (ECL) Inverters

Please use this identifier to cite or link to this item: http://inet.vidyasagar.ac.in:8080/jspui/handle/123456789/747

Full metadata record

DC Field	Value	Language
dc.contributor.author	Chakraborty, B
dc.contributor.author	Pal, R. R.
dc.date.accessioned	2016-12-22T17:05:21Z	-
dc.date.available	2016-12-22T17:05:21Z	-
dc.date.issued	2007
dc.identifier.issn	0972-8791 (Print)
dc.identifier.uri	http://inet.vidyasagar.ac.in:8080/jspui/handle/123456789/747	-
dc.description	119-123	en_US
dc.description.abstract	This paper presents a synchronous oscillator using a high speed low voltage Emitter Coupled Logic (ECL) inverter. Using the positive feedback the locking range increases, compared to the oscillator without any positive feedback. A maximum improvement (increase) of locking range of around 172% was obtained from circuit simulation as well as from practical circuit, using discrete components. Here the supply voltage requirement is 2.1 volts.	en_US
dc.language.iso	en_US	en_US
dc.publisher	Vidyasagar University , Midnapore , West-Bengal , India	en_US
dc.relation.ispartofseries	Journal of Physical Science;Vol 11 [2007]
dc.subject	Synchronous Oscillation (SO)	en_US
dc.subject	Voltage Controlled Oscillator (VCO)	en_US
dc.subject	Current Controlled Oscillator (CCO)	en_US
dc.subject	Ring Oscillator	en_US
dc.subject	Emitter Coupled Logic (ECL)	en_US
dc.title	Synchronous Oscillator Using High Speed Emitter Couple Logic (ECL) Inverters	en_US
dc.type	Article	en_US
Appears in Collections:	Journal of Physical Sciences Vol.11 [2007]

Files in This Item:

File	Description	Size	Format
JPS11-14.pdf		304.12 kB	Adobe PDF	View/Open

DSpace JSPUI